Home - Research & Innovation - Staff - P - Content

Philippe Lorenzini

Philippe Lorenzini


Program:Teachers

Sex:Male

Professional:

Title:Professor

Email:philippe.lorenzini@polytech.unice.fr


Education

(1) June 1987: Master 1Physics of semiconductor and electronics devices, (University of Montpellier - France ) .

(2) June 1988: Master 2 Materials for microelectronics and micro Ionics (University of Montpellier - France), Rank 1.

(3) Sept. 1992: PhD. University Montpellier - France,multi-configuration of DX centers in AlxGa1-xAs compounds.

(4) Nov 2004: Habilitation à diriger les recherches, University of Nice-Sophia Antipolis – France.

Selected Publications (2011-2013)

(1) F. DUHEM, F. MULLER, Ph. LORENZINI, "Reconfiguration time overhead on FPGA : Reduction and cost model". IET Computers and Digital Techniques, August 2011.

(2) F. Duhem, N. Marques, F. Muller, H. Rabah, S. Weber, P. Lorenzini, "Dynamically Reconfigurable Entropy Coder for Multi-Standard Video Adaptation Using FaRM", Microprocessors & Microsystems journal, 2012.

(3) F. Duhem, F. Muller, P. Lorenzini, "Reconfiguration Time Overhead on Field Programmable Gate Arrays: Reduction and Cost Model", IET Comput. Digital Tech. 6 (2) (2012) 105–113.

(4) F. Duhem, N. Marques, F. Muller, H. Rabah, S. Weber, P. Lorenzini, "Dynamically Reconfigurable Entropy Coder for Multi-Standard Video Adaptation Using FaRM", Microprocessors and Microsystems 37 (2013) 1–8.

(5) DUHEM, F. MULLER, Ph. LORENZINI, "FaRM : Fast reconfiguration manager for reducing reconfiguration time overhead on FPGA". in Proc. of the 7th International Conference on Reconfigurable Computing : Architectures, tools and applications (ARC’11), Berlin, Heidelberg, 2011. Springer-Verlag, p.253–260. Belfast, United Kingdom, 23-25 March 2011.

(6) F. DUHEM, F. MULLER, Ph. LORENZINI, "Methodology for designing partially reconfigurable systems using transaction level modeling". in Proc. IEEE Design and Architectures for Signal and Image Processing (DASIP), Tampere, Finland, November 2-4, 2011. Poster Session 2 "Reconfigurable Systems & Tools for Signal & Image Processing".

(7) F. DUHEM, F. MULLER, Ph. LORENZINI, "Dynamic and partial reconfiguration transaction-level modeling in system C". in Colloque GDR SoC/SiP (System On Chip - System In Package), Lyon, France, 15-17 juin 2011.

(8) F. DUHEM, F. MULLER, Ph. LORENZINI, "Transaction-level modeling of dynamically reconfigurable systems using system C". in Proc. Sophia Antipolis MicroElectronics (SAME’2011), Poster session, Sophia Antipolis, France, October 12-13, 2011.