Biography

Zhen GAO received his BS, MS and PhD degree in Electrical and Information Engineering from Tianjin University, China, in 2005, 2007 and 2011, respectively. From 2008 to 2010, he was a visiting scholar in GeorgiaTech. From 2011 to 2014, he was an assistant researcher in the Wireless and Mobile Communication Research Center in Tsinghua University, China. Now he is an Associate Professor of School of Electrical and Information Engineering at Tianjin University, and his focus is fault-tolerant signal processing and blockchain technology.

Education

Ph D (Communication and Information Systems), Tianjin University, 2011

MS (Signal and Information Processes), Tianjin University, 2007

BS (Electrical and Information Engineering), Tianjin University, 2005

Research Interests

(1) Reliability evaluation and fault tolerance design for digital signal processing.

(2) Key technology of Blockchain and its application in wireless networks.

(3) Software defined radio and wireless communication systems

Selected Publications (2015-2022)

(1) Zhen Gao, Jinchang Shi, Qiang Liu, et al., Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Accepted, Dec. 2022.

(2) Zhaohui Guo, Zhen Gao*, Qiang Liu, et al., RNS-based Adaptive Compression Scheme for the Block Data in the Blockchain for IIoT, IEEE Transactions on Industrial Informatics, vol. 18, no. 12, Dec. 2022.

(3) Zhen Gao, Jinhua Zhu, Tong Yan, et al., Fault Tolerant Polyphase Filters-based Decimators for SRAM-based FPGA Implementations, IEEE Transactions on Emerging Topics in Computing, vol. 10, no. 2, Apr-Jun 2022.

(4) Zhen Gao, Han Zhang, Yi Yao, et al., Soft Error Tolerant Convolutional Neural Networks on FPGAs with Ensemble Learning, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 3, pp. 291-302, March 2022.

(5) Junfei Wang, Jing Li, Zhen Gao*, et al., Resource Management and Pricing for Cloud Computing based Mobile Blockchain with Pooling, IEEE Transactions of Cloud Computing, Early Access, May 2021.

(6) Zhen Gao, Lingling Zhang, Yinghao Cheng, et al., Design of FPGA Implemented Reed Solomon Erasure Code (RS-EC) Decoders with Fault Detection and Location on User Memory, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 6, pp. 1073-1082, June 2021.

(7) Zhen Gao, Lingling Zhang, Tong Yan, et al., Design of SEU-Tolerant Turbo Decoders Implemented on SRAM-FPGAs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 12, Dec. 2020.

(8) Zhen Gao, Jinhua Zhu, Ruishi Han, et al., Design and Implementation of Configuration Memory SEU-Tolerant Viterbi Decoders in SRAM-Based FPGAs, IEEE Transactions on Nanotechnology, July 2019.

(9) Ricardo Gonz´alez-Toral, Pedro Reviriego, Juan Antonio Maestro, and Zhen Gao*, A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-based FPGAs, IEEE Transaction on Computers, Vol. 67, No. 7, July 2018.

(10) Zhen Gao, Ming Zhou, Pedro Reviriego and Juan Antonio Maestro, Efficient Fault Tolerant Design for Parallel Matched Filters, IEEE Transaction on Circuit and System II, Vol.65, No.3, March 2018.

(11) Zhen Gao, Qingqing Jing, Yumeng Li, Pedro Reviriego and Juan Antonio Maestro, An Efficient Fault-Tolerance Design for Integer Parallel Matrix–Vector Multiplications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.26, No.1, Jan. 2018.

(12) Zhen Gao, Pedro Reviriego, Zhan Xu, Xin Su, Ming Zhao, Jing Wang, and Juan Antonio Maestro. Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.24, No.2, Feb. 2016.

(13) Zhen Gao, Pedro Reviriego, Zhan Xu, Xin Su, Jing Wang, and Juan Antonio Maestro. Efficient Coding Schemes for Fault-Tolerant Parallel Filters, IEEE Transaction on Circuit and System II, Vol.62, No.7, July 2015.

(14) Zhen Gao, Pedro Reviriego, Wen Pan, Zhan Xu, Ming Zhao, Jing Wang, and Juan Antonio Maestro. Fault Tolerant Parallel Filters based on Error Correction Codes, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.23, No.2, Feb. 2015.

Selected Awards and Honors

(1) Elsevier China's highly cited scholar, 2020, 2021

(2) DFT2021 Best Paper Award

(3) Tianjin University "Peiyang Scholars for Young Teachers", 2016

Teaching Experience

(1) Integrated Circuits Design for Communication Systems

(2) Blockchain Technology and Its Application

(3) Satellite Communications

(4) Wireless Communications